Integer accelerator workbench
Configure a GEMM tile and inspect its execution, numerical error and memory traffic.
Candidate tradeoffs
Click a point to inspect a trade-off.
Lower and left is
better. Error remains a hard constraint.
Quantized classifier and accelerator
Run integer inference and compare the corresponding banked-memory accelerator configurations.
Search comparison
Compare adaptive search, random sampling, and a fixed engineering heuristic under the same evaluation budget.
Published multi-seed results
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Hardware measurements
RTL simulation, formal checks, synthesis and routed timing reports with source hashes and toolchain details.
Architecture reference
Workbench controls, arithmetic definitions and model assumptions.
Workbench controls
- Choose a brief. Each kernel has a latency, resource, and numerical-error budget.
- Change the architecture. Bigger arrays add parallelism, but also cost more and need data faster.
- Run an evaluation. Inspect a processing element and step through the actual integer computation.
- Challenge the design. The adversary picks the worst of four defined workload perturbations.
- Ask for a proposal. Compare the architect’s measured candidate, apply it, and rerun.
- Open Evidence. See the RTL, independent tests, synthesis, physical-design results, and limitations.
Model components
ECE: a synthesizable signed streaming outer-product array, optional product register, finite-width accumulation, synchronous reset, and valid/ready flow control.
Computer architecture: host-scheduled tiles, scratchpad cache model, transfer accounting, memory stalls, utilization, tile reuse, and constrained design-space exploration.
ML systems: integer quantization against a floating-point GEMM oracle, per-tensor versus per-output-channel weight scaling, numerical outliers, and surrogate-guided search.
Research: independent differential tests, intentional defect detection, bounded invariants, standard-cell synthesis, physical-design evidence, matched-budget baselines, reproducible seeds.
Definitions and assumptions
Related work
The Workbench uses a fixed parameterized RTL tile and an analytical memory model. The System lab has a separate banked-memory controller and trained classifier.