SILICON / SIEGETHE ADVERSARIAL CHIP LAB Source ↗
ECE × COMPUTER ARCHITECTURE × MACHINE LEARNING

Make every cycle count.

Design a tiny accelerator. Find its limits. Improve it with evidence.

YOUR DESIGN, UNDER PRESSURE0 of 3 design briefs verified
02 / LIVE FABRIC
Pixel-art circuit island with ceramic chips and copper paths
4 × 4 MAC ARRAYOUTPUT STATIONARY
READY TO EVALUATESelect a processing element to inspect it
CYCLE 0
A cycle-stepped view of the first output tile. Memory stalls are included.
THE DESIGN BRIEF

The adversary searches four stress cases.
DESIGN SPACE

There is no single best chip.

Run the architect to compare candidates.
Your design Evaluated candidate Pareto frontier

Click a point to inspect a trade-off.
Lower and left is better. Error remains a hard constraint.

FROM ML ACCURACY TO RTL TRANSACTIONS

Make the whole system accountable.

A real trained classifier. A banked-memory accelerator. Independent evidence connecting the two.

Loading the trained model and hardware evidence…
CONTROLLED EXPERIMENTS

Let the measurements argue.

Compare adaptive search, random sampling, and a fixed engineering heuristic under the same evaluation budget.

BEST OBSERVED OBJECTIVE ↓Same start · same budget · same workload
Adaptive surrogateRandom samplingFixed heuristic

Reproducibility beats a lucky run.

Loading the published multi-seed experiment…

SHOW YOUR WORK

Pretty pixels. Inspectable proof.

Real hardware tools run remotely. Their results live here alongside the exact scope, toolchain, and limitations.

Loading hardware evidence…
THE FIELD GUIDE

Understand the trade-off.

A short path from “what is a MAC?” to the assumptions behind this experiment.

Three minutes in the foundry

  1. Choose a brief. Each kernel has a latency, resource, and numerical-error budget.
  2. Change the architecture. Bigger arrays add parallelism, but also cost more and need data faster.
  3. Run an evaluation. Inspect a processing element and step through the actual integer computation.
  4. Challenge the design. The adversary picks the worst of four defined workload perturbations.
  5. Ask for a proposal. Compare the architect’s measured candidate, apply it, and rerun.
  6. Open Evidence. See the RTL, independent tests, synthesis, physical-design results, and limitations.

The engineering contract

ECE: a synthesizable signed streaming outer-product array, optional product register, finite-width accumulation, synchronous reset, and valid/ready flow control.

Computer architecture: host-scheduled tiles, scratchpad cache model, transfer accounting, memory stalls, utilization, tile reuse, and constrained design-space exploration.

ML systems: integer quantization against a floating-point GEMM oracle, per-tensor versus per-output-channel weight scaling, numerical outliers, and surrogate-guided search.

Research: independent differential tests, intentional defect detection, bounded invariants, standard-cell synthesis, physical-design evidence, matched-budget baselines, reproducible seeds.

A model with visible boundaries.

Research that shaped the lab

Gemmini ↗Full-stack accelerator evaluation; array results alone miss system effects.Timeloop ↗Make data movement and mapping assumptions explicit.SmoothQuant ↗Outliers matter in quantization. This lab uses simpler symmetric quantization, not SmoothQuant.RTL-OPT ↗Correctness and real PPA evaluation must accompany RTL optimization.Dr. RTL ↗Tool-grounded optimization is established research. Our focus is interactive adversarial co-design.OpenROAD ↗Open RTL-to-layout tooling and reproducible physical-design analysis.

This project makes no claim to outperform industrial EDA or to have invented autonomous chip design. Its contribution is a coherent, inspectable co-design environment under a small compute budget.

INSPECT